The present invention relates to a resistance dividing circuit employed in a semiconductor integrated circuit and a method for manufacturing the resistance dividing circuit, using a salicide process.
A resistance dividing circuit has such a shape as shown in FIG. 6 by way of example, illustrated in plan view. The resistance dividing circuit shown in FIG. 6 has a configuration wherein contact plugs are respectively connected to plural points of a resistance wiring composed of polysilicon, and metal wirings are respectively connected to the contact plugs. The metal wirings serve as connecting terminals of the resistance dividing circuit. Arbitrary resistances can be obtained by selecting the connecting terminals. The resistance dividing circuit having such a configuration has been described in a patent document 1 (see Japanese Patent Publication No. Hei 5(1993)-30072).
In the resistance dividing circuit disclosed in FIG. 6, however, the contact plugs are directly connected to their corresponding polysilicon layer. Such a resistance dividing circuit as disclosed in FIG. 6 is normally configured such that its upper side is covered with an insulating layer. Thus, in order to form the contact plugs, there is a need to form contact holes in the insulating layer lying on the polysilicon layer. Upon opening the contact holes, it is hard to provide a suitable etching selection ratio between the insulating layer and the polysilicon layer because the insulating layer is normally SiO2. Therefore, there is a high fear that etching will extend to the polysilicon layer upon opening of the contact holes. In doing so, the resistance of a portion where each of the contact plugs and the polysilicon layer contact varies.
In order to solve such a problem, the polysilicon layer and each contact plug may be connected with a silicide layer interposed therebetween. Since, however, the silicide layer is a material low in resistivity, the values of resistances of portions where the silicide layers are formed, decrease when the silicide layers are formed on the polysilicon layer corresponding to the resistance wiring. Even if the decreases in resistance value are slight, they are piled or built up since the contact plugs are arranged in series on the resistance wiring. Thus, the decreases in resistance value of the circuit as a whole cannot be ignored.